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IBM High Level Assembler for z/OS and z/VM

Showing 41

Support JXH and JXLE for exit t the beginning of a loop

Support JXH and JXLE for, e.g., ASMEXIT, DO WHILE, DOEXIT, IF, for testing loop termination at the beginning.
2 days ago in IBM High Level Assembler for z/OS and z/VM / Toolkit 1 Under review

Some SuperC options should cater for longer lines

A number of SuperC compare options are currently rejected for datasets with an LRECL > 256: ISRS013W CERTAIN "DO NOT PROCESS" OPTIONS ARE REJECTED DUE TO LI NE LENGTHS > 256. OPTIONS RESERVED FOR PROGRAM SOURCE DATA. ISRS016W MOVE LINE DETEC...
almost 4 years ago in IBM High Level Assembler for z/OS and z/VM / Toolkit 2 Not under consideration

True length of DSECT

There should be a method (perhaps a new parameter) that would cause the "length" attribute of a DSECT to return the actual size of the dummy section, rather than simply returning a value of 1.
over 8 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 3 Not under consideration

Structured Programming Macros: support parenthetical grouping of logical conditions via parentheses

Support for parenthetical grouping of logical conditions is currently only possible by using the ANDIF and ORIF operators. This is because the Structured Programming Macros do not support the use of parentheses to specify logical hierarchy of cond...
over 8 years ago in IBM High Level Assembler for z/OS and z/VM / Toolkit 1 Not under consideration

Allow wildcards in SuperC batch member selection

Using SuperC Search-For from the ISPF panels allows members to be selected using '*' and '%' wildcards, i.e. like '*SP3%' as a membername. It would be very useful if the same format could be used in SELECT statements in the JCL SYSIN dataset
over 9 years ago in IBM High Level Assembler for z/OS and z/VM / Other 4 Future consideration

Flag RX instructions with index but no base register

It has been a common malpractice since more than half a century not to use a base register but the index register in rx instructions, e.g. L Ra,100(Rb) instead of L Ra,100(,Rb). Historically, this implied some performance penalty (AFAIR), nowadays...
over 1 year ago in IBM High Level Assembler for z/OS and z/VM / Assembler 2 Not under consideration

New extended mnemonics needed for branches/jumps following TMLL and friends

New extended mnemonics are needed for "branch/jump [not]mixed" instructions to be used following the newer Test Under Mask instructions. The older TM instruction never sets CC=2, so the older branch/jump [not]mixed mnemonics (JM, JNM and similar) ...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 2 Not under consideration

Change ASMA033I severity from 0 to 4

Our product requires 241 separate assemblies. When reviewing a gen, we take closer looks at any assembly having a non-0 completion code. ASMA033I errors currently are SEV 0. That means that they get missed when a GEN is reviewed. If they were chan...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 4 Future consideration

Permit named PUSH/POP statements

When the assembler reaches an END statement, and there remains unPOP'd PUSH USINGs, it issues ASMA138W . Well, in large complex assemblies, finding the unPOP'd PUSH or PUSHs can be rather a challenge. In my own coding, I have solved that by replac...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

Fully support 32-bit EQUs (maybe even 64-bit EQUs as well)

The assembler's support of 32-bit EQUs is arcane, to say the least. Consider: EQU1 EQU X'80000000' EQU2 EQU X'80000000'+1 EQU3 EQU X'7FFFFFFF'+1 The EQU1 and EQU2 statements are fine.The EQU3 statement gets flagged with ASMA074E. I do understand t...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 3 Not under consideration

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