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We have assessed this requirement. We have no current plans for this to be implemented and so this requirement is being declined at this point. The requirement will be kept in the RFE system and might be reassessed in the future. You also have an opportunity to resubmit in twelve months time if you wish it to be reconsidered then.
Due to processing by IBM, this request was reassigned to have the following updated attributes:
Brand - Servers and Systems Software
Product family - Transaction Processing
Product - CICS Transaction Server
For recording keeping, the previous attributes were:
Brand - WebSphere
Product family - Transaction Processing
Product - CICS Transaction Server
Chuck, thank you for your comments.
Making SDT threadsafe is an aspiration, but in reality the code is highly optimised and removing the QR affinity would very likely involve a re-write of the SDT code. So its another one that I would not hold your breath for. An easier proposition may be CFDTs.
Making shared data table access threadsafe would help facilitate my shop's ability to save a hugh amount of cpu by eliminating function ships via QOR and FOR elimination.. I would like to collapse 6 cics regions (4 AORs 1 QOR 1 FOR) into just 1 region. Now that my shop is running cics ts 4.2, the Temp Storage main EDSA constraint will no longer occur. But, my shop is using shared data tables for both cpu savings (by eliminating file function ships), and VSCR (avoiding the use of LSR virtual storage bnuffers in the cics address space). If I collapse the 6 cics regions into one, I would have to run most of the programs threadsafe to avoid QR tcb constraint. I would then either have to change the file definitions back to NOT specify SDT to obtain efficient threadsafe processing, or, keep the files defines to use SDT for VSCR, but consume a lot of cpu doing mvs tcb switches. If SDT access is made threadsafe I could 'have my cake and eat it too'. I would still get the VSCR needed to collapse all the regions into just one. And, I could run the application programs threadsafe, and not incur mvs tcb switches.