provide 64-bit addressing capability for CICS applications

The customer's C/C++ applications get to a size where they urgently need 64-bit addressing support within CICS. The customer's requirements are focused on how existing CICS applications could benefit from 64-bit adressspaces without being modified. They recommend an implementation that is based on CICS subspace technique.
The requirement in more detail is:
- CICS applications should run in subspaces within a 64-bit address mode adressspace
- each subspace of this kind should have a max of 2 GB
- Transaction isolation is required (because of subspace design)
- there should be an address virtualization mechanism in CICS that ensures that the application (running in a subspace) can use
virtual storage ranging from 0 to 2GB
This design would have 2 major advantages:
- each transaction has 2 GB available for its own
- existing applications do not have to be changed.
Some of the problems the customer suffers today with the 31-bit addressing limitation in CICS are:
In the production environment the load modules get to a size that would require multiple CICS regions in parallel. However, the CICS ISC communication produces significant overhead that adds to CPU cycles and SW-license costs, as well as additional administration work.
In the development environment one major problem is that IBM Debug Tool adds additional resource requirements to the application programm being debugged. In consequence they just cannot debug their programms in a proper way.