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Status Not under consideration
Workspace z/TPF Product Family
Categories z/TPF
Created by Guest
Created on Apr 26, 2017

RELATED IDEAS

Optimize macro trace and function trace buffer allocation

Could IBM review the effect of trace buffer allocation on system performance?
Currently both the macro trace and function traces are split between regular and extended buffers, so any update requires access to storage in two different cache lines.
By combining both regular and extended buffers they would fit into a single 256 cache line buffer:
macro trace function trace
regular buffer size 96 128
extended buffer size 120 136
Total 216 264
Less 8 byte linkage ptr 208 256

This calculation works because each regular trace buffer has an 8 byte area reserved for the address of its extended trace buffer, removing this storage means the current function trace data would fit exactly in a 256 cache line buffer.

The current zSeries CPU hardware places great importance on efficient use of L1, L2 and L3 cache so this suggestion might be worth testing?

Idea priority Medium
  • Guest
    Reply
    |     May 8, 2017

    IBM does not intend to implement this request. Combining both regular and extended buffers may cause a performance impact. If the extended trace options are not always on then overhead occurs which causes a performance impact. The regular and extended buffers were purposely separated for performance reasons.

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