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Status Future consideration
Workspace z/TPF Product Family
Categories z/TPF
Created by Guest
Created on Jan 30, 2020

RELATED IDEAS

Use XWBs for MPIF and IPC

In previous exchanges with IBM re: XWB usage, it was noted that MPIF and IPC were not changed via PJ45291 to use XWBs. That being the case, we will not be able to reduce frame usage even after the PJ45291 is applied, which somewhat defeats the purpose of that APAR.
If you look at CASE # TS003221079, where we couldn't IPL RESA due to an out of frame condition when trying to IPL the processor, you'll see why we can't reduce the # of frames. In this scenario, we have a necessary local mod to queue IPC requests, and when the processor is IPL'd, those are released. In this scenario, they came flooding in, exhausting the frames in the system. We understand that if IPC is changed to use XWBs, we would need to change that modification to handle 8 byte core addresses in the queuing. IBM indicated that if we want MPIF and IPC support to be changed to use XWBs, we should open an RFE.

Idea priority Medium

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