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My ideas: Assembler

Showing 21

True length of DSECT

There should be a method (perhaps a new parameter) that would cause the "length" attribute of a DSECT to return the actual size of the dummy section, rather than simply returning a value of 1.
over 8 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 3 Not under consideration

Flag RX instructions with index but no base register

It has been a common malpractice since more than half a century not to use a base register but the index register in rx instructions, e.g. L Ra,100(Rb) instead of L Ra,100(,Rb). Historically, this implied some performance penalty (AFAIR), nowadays...
over 1 year ago in IBM High Level Assembler for z/OS and z/VM / Assembler 2 Not under consideration

New extended mnemonics needed for branches/jumps following TMLL and friends

New extended mnemonics are needed for "branch/jump [not]mixed" instructions to be used following the newer Test Under Mask instructions. The older TM instruction never sets CC=2, so the older branch/jump [not]mixed mnemonics (JM, JNM and similar) ...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 2 Not under consideration

Change ASMA033I severity from 0 to 4

Our product requires 241 separate assemblies. When reviewing a gen, we take closer looks at any assembly having a non-0 completion code. ASMA033I errors currently are SEV 0. That means that they get missed when a GEN is reviewed. If they were chan...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 4 Future consideration

Permit named PUSH/POP statements

When the assembler reaches an END statement, and there remains unPOP'd PUSH USINGs, it issues ASMA138W . Well, in large complex assemblies, finding the unPOP'd PUSH or PUSHs can be rather a challenge. In my own coding, I have solved that by replac...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

Fully support 32-bit EQUs (maybe even 64-bit EQUs as well)

The assembler's support of 32-bit EQUs is arcane, to say the least. Consider: EQU1 EQU X'80000000' EQU2 EQU X'80000000'+1 EQU3 EQU X'7FFFFFFF'+1 The EQU1 and EQU2 statements are fine.The EQU3 statement gets flagged with ASMA074E. I do understand t...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 3 Not under consideration

Assembly Listing Headers - Four lines of USINGs information is not enough

Currently, the page headers area for Assembly listings is limited to 8 lines: title line, page number, column headers and... from two to four lines of active USINGs information. I use named USINGs a LOT! So much so, that I frequently blow through ...
over 2 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

Improve ability to define structures with power-of-2 size

When writing assembler code, it is often desirable or even necessary to define a structure with a length that is an integral power of 2. Reasons for such might be to avoid crossing a cache-line boundary; to be able to allocate an array of structur...
over 8 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

Option to check instruction-to-field mismatches

Looking for an option which when specified would have HLASM report instances where the instruction mismatched the data that it would operate on. Like "check that I am using instructions that match the data length of the field".
about 9 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

Allow fields >= 64k

The assembler currently only supports the definition of fields less than 64k bytes in length. The assembler should be revised to support the definition of fields greater than or equal to 64k bytes in length.
almost 9 years ago in IBM High Level Assembler for z/OS and z/VM / Assembler 1 Not under consideration

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